Different communication protocols have different requirements with regard to ordering of transactions. For example, the Peripheral Component Interconnect Express (PCI Express™ (PCIe™)) protocol for links based on the PCI Express™ Specification Base Specification version 2.0 (published Jan. 17, 2007) (hereafter the PCIe™ Specification) provides for ordering requirements with regard to posted transactions such that one posted transaction cannot pass an earlier posted transaction. A posted transaction is a transaction in which a requestor does not receive a completion message when the transaction successfully completes. In contrast, for a non-posted transaction a requestor expects to receive a completion message when the transaction is correctly performed. Ordering rules for PCIe™ links require transactions following a posted transaction to push the posted transaction, generally until the posted transaction reaches a processor core. If the earlier posted transaction is an interrupt, current systems enforce such ordering rules by pushing transactions through an interconnect until the interrupt transaction is registered within a local advanced programmable interrupt controller (APIC) of the processor.
While these rules ensure that interrupts are provided to a processor, it can delay later transactions if the processor is in a low power state and therefore takes a long time to accept the interrupt and return a completion to indicate that it has been seen. That is, when a processor is placed in a low power mode, it cannot receive such interrupts and return a completion promptly. It is anticipated that in future systems with advanced processors, more opportunities will be provided for power management states in which processor cores can lose clocks and power. Furthermore, the deeper the low power state that is entered, the longer it takes to recover to an operable condition. As a result, the time for an interrupt to be registered in the processor can be relatively long. Furthermore, platform power management techniques can result in aligning interrupts to an operating system timer tick, such that a number of interrupts can be grouped together.
Thus when adhering to the ordering requirements of a given communication protocol, particularly when a processor or part thereof is placed in a low power state, a bottleneck can occur. As a result, latency sensitive devices such as peripheral devices coupled to the processor that begin a communication cycle via an interrupt, can be adversely affected. For example, a universal serial bus (USB) device may have a frame time of approximately 20 microseconds (μs). However, it may take a processor core a longer time period to wake from a low power state. Thus using current interconnect ordering rules, adverse effects can occur.